The invention relates to testing a plurality of semiconductor devices, and more specifically to testing semiconductor devices on an integrated circuit.
The fabrication of integrated circuits (ICs) is imperfect and subtle changes in the fabrication process will change the performance of the ICs across wafers and batches from the foundry. To monitor and characterize these changes in the process, on-chip circuitry is useful. Accurate measurement of on-chip components typically requires several pins at the IC boundary for calibration purposes. The use of several pins, however, increases IC area while also increasing package and printed circuit board (PCB) complexity. If area and system complexity increase, then the associated system costs could rise as well.